Synchronizing generator



July 7, 1953 A. E. woLFE, JR

sYNCHRoNIzING GENERATOR n 135" Sheetsfsheet 1 Filed Dec. 18, 1950l www@ July 7, 1953 A. E. woLFE, JR

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July 7,1953 A. woLFE, JR 2,644,887

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.BYNclmoNIzING GENERATOR 15 Sheets-Sheet Filed Dec. 18, 1950 INVENTOR.-' v

` Mw* ai wf@ Patented July 7, 1953 `bymes-ne assignments, to Computex-,'SResearclx. Corporation .of California, a corporation "of Delaware -f-ApplicationDec'ember 18, 1950, Serial NOJ201y375 .16 'Jlaims. (Cl. v250--2/7 1 The present inventionlrelatesf to synchronizing fg'enerators, and ymore :-.iparticularly :to :anovel imeansiforvproducing a pluralityof complex' timing fpulses.

`Wl1i1e 'the present invention: is` applicable to synchronizing generatorsfin 4I general, yit fis :parlticularly, designed' fori producing the 4conventional 'synchronizing pulses :required :in television `systems.

In-L'such systems,I at-lthe broadcasting station, a fsynchronizing Sgenerator is "employed Eto `furnish 'pulses lfor fthe sweep generators scanningmthe "cameras tube,'and'1also ttor pro ducethe' 'synchronizfing pulses f'added to 'the composite lvideo signal transmitted *on (the -"picture cai-rien The `latter pulses i are separated from 1 the composite video fsignallat the receiver lto provideltlie/timing for the sweep lgenerators that -scan'lthescreen Hof the picture tube,rthus making it-possibleforthe scanning' ati-the receiver -to i be synchronized with the "scanningfat the transmitter.

' Briefly, 'my invention makes use o'f-af timing-device, infthis casea constant'y frequencyfoscillator, providinga series of timing pulses. "Inheselpulses 'are' counted by a series-` of"counters,ian"d When-la predetermined numberor count is 'reached, 4fa l`-sufitchingcircuit is operated 1 to fprovidel'e'ither a r`liighorllovv voltage output. f Because ofthes'peed 'at -Iv'vhich the counters Vland '-switching circuits *must operate, elec-tronic instead-l f Z4'electro-mechan-ical"countersandf'svvitches 1 areiused. l l'Additionally, in order to reducethe requiredi'number Y ofV individual counting elements' I'have Vused -the teachings of symbolic logic to. combineloutputs'of A"thevariouscounters in ainovel manner. Thus, I may"fadd by-symbol1c logic;therebyperforming the'processfofllo'gical addition,an`d- I may multif`plylloyfY symbolic-1o gie, therebytperforming logical multiplication lThecircuitsfor'performingzthese processesfmaylbetermed .logicalnetsor flogical i networks. These terms are further defined Ihereinafter.

lione featureofthe`;present"synchronizingfgeneratorfarrangement iis thattlde` .timing rofl all -the vleadingiand trailing 'edges of f the waveforms 1ere obtained as thezresulti of: specflclcountsappearing -.infa cascade of counters whichareactuated by pulses' from affixed vfrequencyfsource.

Another '.feature of the arrangement is Icon :cerned withzproviiding a cascade lofcouritersfeach :fof the '.-counters having 'radices zicho'sen to most fsimply generate.thelcyclicalcoun-ts' corresponding to the edges of the waveforms.

, EStill anotherfeatureis'c'onoerned lwithfprovidlingua -complexzwaveformias'fthe.outputf'of Valflip- `on separate lines. yco-mloin'e'd inntworksto"generate trigger pulses flop circuit ywliichis.adapte'd' tol bei' triggeredinto one state or'the other'as tlie result of Specific counts,J in. aplurality of counters, 4corresponiirig desired.

uStill-another featureof the inventioniis'concerned VWith. novl means 'f or v'combining voltages,

corresponding to specific counts in'apl'ural'ity'of counters, into logical -propositionsused sforconitrolling 'nip-flops 'which C'generate `the 4desired waveform. l

"Briem thepresent irvention"c'omprises `ailixed high frequency ypulsesource feeding az'ca'scade of counters having nonuniformrradices. Specic counts of vthe counters aresensed'a'shi'glilvoltages These voltages-are *logically which fco'xitrlthe state --of'"output"flip-flopsi 4The output waveforms desired arev 'obtained' by Lsensing "This inventionwill be better lunderstood from the following "description taken in 'connection With "the accompanying drawings'v in-lwh-i'ch:

"F'iguref'l is aschematic block diagram "showing ink simplied form the'ap'paratusfinvolvingthe mveritionas'applied' to asynchronizinggenerator Y ':foratelevisloxrsystem.'

Figure "2ais"v aCg-rap'h vsl'low'ingthe lLvvavefoifmfoi' the sync pulses generated on one output Ilifne from the generator.

Figure -2`b-is1af "graph-'ishowiug-the waveformlof the horizontal drive pulses generatedonianother --outputline fromlthe' generator.

*Figure2c`is'1agraph showingthelwaveformifof the vertical drive pulses generatedionlstill another output 'line fromthefgenerator.

Figure 2d is2 a fgraphfshowing .the'waveform of `thefrnix'ed lolankin'g lpulses #generated oniafinal output line from the generator.

Figure s53 Y is 4a italle of the `number .fcontents o `tlre-"counters-thatf deline inparticularltheleading and trailing edges of the syncplseslshowndn f'Ivisu'refli us 'ad-table Noff-'the numberlcontents-:of the counters that dene in-fparticular-lthelead- 4ing-'and trailing-#edges of fthe lblankingplses lshown'ini-Figure'12d.

Figi'iref'lisea schematic lblockildiagramsofsthe counters and the digit contents whichare' toflbe 's'ensedfasfoutputs'ftherefromdon ysepa'ratew'li'ne's.

ff-which-Jareireferred V"to infexplainimg'itlieroperation of the C counter nip-flop.

Figure 7a is a block diagram of the sync output flip-flop together with logical equations defining the triggering input for its control grids.

Figure '7b is a block diagram of the horizontal drive output nip-flop together with the logical equations defining the triggering inputs for its control grids.

Figure '7c is a block diagram ofv the vertical drive output flip-flop together with the logical equations defining the triggering inputs for its control grids.

Figure 7d. is a block diagram of the mixed blanking output flip-flop together with the logical equations deflning the triggering inputs for its control grids.

Figure 8 is a block diagram of a flip-fiop used for generating a counting interval together with its trigger logical equations.

Figure 9a is a block diagram of the A parallel counter together with the logical equations defining the triggering inputs for each of its fiipflop stages.

Figure 9b is a table of the states of the fiipfiop stages characteristic of each digit content of the A counter.

Figure 9c is a schematic circuit diagram of the counting logical net and digit output logical net for the A counter.

Figure 10a is a block diagram of the B parallel counter together with the logical equations defining the triggering inputs for each of its flipfiop stages.

Figure 10b is a table of the states of the flipflop stages characteristic of each digit content of the B counter.

Figure 10c is a schematic circuit diagram of the counting logical net and digit output logical net for the B counter.

Figure 11 is a block diagram showing a more detailed arrangement of the D counter and the Adigit output lines required therefrom.

Y. a number in the D counter.

Figure 13a is a block diagram of the E parallel counter together with the logical equations defining the triggering inputs for each of its flip-flop stages.

Figure 13b is a table of the states ofthe flipflop stages characteristic of the number content of the E counter.

Figure 13e is a schematic circuit diagram of the counting logical net and digit output logical net for the E counter.

Figure 14a is a block diagram of the F parallel counter together with the logical equations defining the triggering inputs for each of its flip-flop stages.

Figure 14b is a table of the states of the flipflop stages characteristic of the number content of the F counter.

Figure 14C is a schematic circuit diagram of the counting logical net and digit output logical net for the F counter. v

Figure 15a is a block diagram of the G parallel counter together with the logical equations defining the triggering inputs for each of its flipfiop stages.

Figure 15b is a table of the states of the flipflop stages characteristic of the number content of the G counter. l

Figure 15c is a schematic circuit diagram of the counting logical net and digit output logical net for the G counter.

Figure 16 is a logical net for generating the triggering inputs to the sync fiip-flop.

Figure 17 is a logical net for generating the triggering inputs to the horizontal drive flipfiop.

Figure 18 is a logical net for generating the triggering inputs to the vertical drive, mixed blanking, and the counting interval flip-flops.

Referring first to Figure 1, a general block diagram is shown of the preferred embodiment of the synchronizing generator of the present invention along with associated equipment as required for a television system.

Here a pulse generator I0 emits square wave pulses P at a fixed rate of '787.5 kc. s. into a cascade of counters II. Counters II are comprised in the main of counting logical nets IIa controlling the states of counting flip-flops IIb. In order to provide certain digit contents of counters II, corresponding to the leading and trailing edges of the rectangular pulses to be formed, the states of the counter flip-flops I Ib, as sensed on outputs I2, are fed into a digit output logical network I3 where they are combined such that each of the lines I4 therefrom, when energized, corresponds to a specific digit, or range of digits.

The signals corresponding to these digit outputs are then further combined in a logical net- Work I5 to form triggering signals which control the change in states of the sync flip-flop SI, the mixed blanking flip-flop MI, the vertical drive flip-flop VI, and the horizontal drive flipflop HI. The voltage waveform outputs from the vertical drive flip-flop VI and the horizontal drive flip-fiop HI are fed through a first pair of cathode followers I6 and I1, respectively, to the sweep generators I8 which control the scanning of camera I9. The waveform outputs from the sync flip-flop SI and the mixed blanking flipflop MI, on the other hand, are fed through a second pair of cathode followers 20 and 2l, respectively, to the mixing amplifier 22 where they are combined with the video signal from camera I9. The composite output signal from the mixing amplifier 22 is sent to a video transmitter (not shown) via video output line 24,

In Figures 2a, 2b, 2c, and 2d the conventional waveforms desired to be generated by means of output flip-flops SI, MI, VI, and HI are shown. It should be noted that the output pulses all have the same amplitude but differ in pulse width or waveform. The desired amplitude is obtained by means of the cathode followers associated with each of the fiip-flops.

The sync pulse generated by flip-fiop SI is the most complex waveform and will be described first. As is well known, the function of this waveform is to keep the receiver locked in with the transmitter scanning by maintaining correct timing of the vertical and horizontal scanning motions.

According to present television practice, 30 frames of a picture are transmitted per second. Each frame is comprised of 525 horizontal scanning lines, the odd numbered lines of which are presented in one field followed by a second field made up of the even numbered lines. Since there are two fields per frame, this sets the vertical synchronizing pulse frequency needed to synchronize the fields at 60 cycles per second, and the horizontal synchronizing pulse frequency needed to synchronize each horizontal line at 15,750 cycles per second.

In the present invention the single timing pulse source I0, having a frequency output of nieuwe?? counts-are repeatedevery`1/30 v`of f a-fseconciy to provide f the 1 succeeding frame '-sync" pulses. n

As is `rapparent from Vthe Afdravi'rin'gs, the f counts `'in lcolumns 30 yand y"13| ycorrespond "to the' numbers assigned to the pulse edgesfof vthe'yain'e- `for'msshown-inFigure-Za. f f

count whichdefines one f frame,`-*thefirst 1 half, 11 through 13 125 represents the "odd field:l interval; andthe -second "half, 131126 through "-26250Yrepresents the evenfeld interval. y y f Aswvillloe noted, 4the countersfresetfto-'O fat the 2625() timing pulse count uand' 'h'ence "count 26250 does not actually exist assuch; but rather :isddciine'dl as the Ocount.

The pulses in each field cazrbe divi-ded broadly into "two intervals, the *rst interval designated byjthecreference` character "2 8v includes the'pulses required `for vertical synchronization; and the vsecond interval designated"29 iscomfprised` of the l pulses' required"for"horizontal synchronization.

' Iteferring to Figures '2a and 3, the Y"pulses Arequired'i'for 4verticalisynchronization -as "den'ed'by interval '23 'in the'odddield vare ytheiirst"on`es vconsidered. These'includea'group of 'sixequalizing pulses followedby aprolonged'vertical"pulse having iive serratiOnS, and 'then six additional /equalizing pulses. The horizontal'syncinterval 29 Whic'h'follows is composed'of av stream of iden- 'tical pulses which recurat axedrate throughcutthe remainderof the iirsteld. y"The second .eldis composed'of a similar arrayof vertical "synchronizing .pulses `followedv by the horizontal ,.of'the equalizing pulses .in-.accordance Withthepresent invention gures out to'be twenty-five units This twenty-five unitspacing is the same `for theleading edges of the, .following .prolonged vertical pulse andits .serrations 4andalso the succeeding equalizingrpulses. vHencethe 25 unit .interval counts, such vas`26, 51,76, etc..jthrough H426, are assigned to thejleading edges of these pulses. YStarting With number 4541,-whichxrepresents the leading edge of the rst horizontal sync .edge ofthe rst equalizing pulse .for-fthe even iieldoccurs. f For this lattereld, as .beforethesuccessive pulse leading edges arel spacedsat 25^ unit rinterval counts such as 13151, 13176,etc-fthrough 13551: .-which denes the leadingedgeofthe last equalizing pulse. The succeeding .horizontal -async `pulsesare spaced at 50unitintervals suchfas 13601,513651,1etc.v and this lrepeatsthrough count 01. Whichxdefinesi the; leadingiedge'sofgthelast 2 75 pulse, the numbers .assigned to thel succeedingV 0 "horizontal sync pulse leading edges. are spaced atr founit/count intervals, suchas counts 501,57511, qnctc. .through 13101. At 13126,`Which.is.25 .units afterV theA last horizontal sync pulse, the leading .365.

pulse in'fthe even field. .ffliiftyfpulsecountsalater, the counters havereset'to 0 andcountl appears again therein, thus .startingxthe cyclical'count 1 for the next frame.

Thus it is seen'that theileading edgesaofvall the sync pulses are temporally spaced'at'either 25 `or 50 unit rcounts apart. .'Forl'purposesaof later discussion these temporal spacings ``willlbe 'referred to :as half-line and whole-lineintervals, respectively.

f 'Referring next tto the trailing .edge .counts` of these pulses, .ity is noted `in Figure .2a :that lthe widthof allthe equalizing pulses are twoun'it counts, hence the ktrailing edge countsforfeach of these pulsesfwhich appear'fin thesa'me row of the table of Figure 3,are noted in column'l by increasingeach oftheleading'edge countsby two. It is understood that each of the rectangularpulseslisaconsidered to be `formed at theend of the unit countperiod 4assigI-iedto'the .leading edgesandaat `theend of the unit'count vperiodvassigned'to the trailing edge.

In ailikemanner, Athe width-ofthe vertical serrated'. pulses is shown tov be -21 'unit'.'countsl lhence vthe trailing .edge counts -shown-in column 3| for these pulses-'are obtainedby- `adding -21 unitsv toeach of the'leading edge counts-showin in column 30.` y f f.

As for the horizontal sync pulses,- they are four .units counts wide, hence the trailing edge counts for these pulses are obtained by addingf4-units'to their leading e'dgefcounts.v Y

f In accordance with.. conventional fpractice it should .he noted that, whereas-the Aleading-edge of the rst equalizingi pulse of the 'odd'eld is spaced a Whole line, 50unit intervalvcount, from the leading edge ofthe precedingy horizontal sync pulse; .the leadingfedgeofthe i'lrst equalizing pulse of the even field is spaced anali-line, or 25 unit interval, from the :preceding horizontal sync pulse.. Onthe yother hand, .theleadingfedge of the last equalizing pulse for the Aoddfieldfis followedby a horizontal .pulsespacedxa half-line interval away,.while'f the .leading edge of the llast equalizing pulse forthe 'even iieldA is followedby a. horizontal (sync .pulse spaced .a yu'zhole-line v'interval away;

The horizontal 'drive L waveform .zemployediffor contro11ing-thecamera horizontallinescanning' .is

p generatedby the: H Iz nip-flop. LThisiwaveformf as shown in'F'igure 2b is identical with the .horlzontalsync. pulses (Figure 2a) ,.in that pulses,.de fined by the sameleadingand trailing .edge num- .ber counts `,given to the;.horizonta1 sync pulses, such as 451, 501, etc., `are found therein.- .But .whereas the horizontal sync` pulses were. restricted .to eertain-number'ranges, the horizontal:drive pulses occur continuously at whole line intervals, i. e., every fifty unitcounts, throughoutxa, frame. The f vertical drive .output waveform` used Afor l controlling the camera vertical scanning is vshown in Figure 2c;r` These vertical vdrive pulses. .occur once each eldor twiceaframe. .It-should be` noted that the leading-edges of these rectangular waveforms are one unitiearlierthan thezrespective .leading `edges "of vthe first .equalizingpulses in the Yodd Aand" even. lfields asi shown inA Figurel2a. Hence the leading edges of therst verticaldrive .pulse is assigned count 0,1an'd the `leadingedgev "of fthe second is assigned count 13125.' Theitrailing edge ofi these waveformsfwhich is .not critical,A has beenfarbitrarilyfsetat counts 808 and 13933, respectively, since as will be noted, these counts most readily' adapt themselves .-toLthe` counts cof the blanking pulsesztolbe'lnextdiscussed.

' retrace time.

.A This waveform (Fig. 2d) is composed of the vertical drive output waveform shown in Figure 2c together with a stream of horizontal blanking pulses inserted therebetween. Referring to the table in Figure 4, the leading edges of the ver tical blanking pulses are assigned numbers and 13125, and the trailing edges thereof are assigned numbers 808 and 13933, these edge counts being identical to those for the vertical drive waveforms.

f On examining the horizontal blanking pulses, it is noted that the leading edge of each of the horizontal blanking pulses occur one unit pulse time earlier than a corresponding horizontal sync pulse. Note for example, horizontal sync pulse leading edge count 13101 (Figure 2a), as com- .pared to horizontal blanking pulse leading edge count 13100 (Figure 2d). In addition it is noted that the latter pulse is twice as wide as the former, i. e., 8 unit counts instead of 4. Thus the trailing edge of each of the horizontal blanking pulses, as shown in column 34 of Figure 4, is defined by the leading edge content thereof in column 33 increased by eight units.

Referring back to the. table of Figure 3, the basic repetitive counting interval for the leading edge of the waveforms is 25 units which is equal to a half-line interval. This indicates that a 25 unit cycle counter would be desirable to give digital output lines which are energized every 25 unit counts.

To obtain a simple 25 unit counter a radix five counter A is provided which feeds its output into a second radix five counter B. The output from the second counter B is then fed into a D counter considered to have a radix of 525. This arrangement of counters is shown in Figure 5.

In addition a counter C which is likewise actuated by the carry from the B counter is employed for keeping track of the half-lines, i. e., whether the half-line counted by carry from counters A and B is the first or last half-line of a whole line interval.

In order to determine the digit lines of these counters required to sense the leading and trailing edge counts previously recorded in columns 30 and 3| of the table in Figure 3, these counts are converted into the non-uniform radix number represented in particular by counters A, B, and D.

To find the digit contents in these counters equivalent to the counts shown in columns 30 and 3|, it is noted that every time the B counter counts to capacity a carry pulse corresponding to a twenty-five unit count is fed into the D counter, increasing this latter counter by one unit. Thus, for example, after the initial 25 unit count from pulse generator l0, the D counter has a 1 therein and on the receipt of the next .pulse from pulse generator I0, corresponding to unit count 26, counter A is made to contain a 1. 'Ihus leading edge count 26 is represented by a digit 1 in counter A, digit 0 in counter B, and digit 1 in counter D. In a similar manner, all the leading and trailing edge counts are converted to a nonunform radix number, so to say, as represented by digits in counters A, B, and D.

'After the D counter has recorded 524 twentyfive unit counts, or half lines, the next carry therein from counter B resets the D counter to 0. Thus it is noted that the D counter resets to 0 at the end of each field.

The leading and trailing edge counts of the blanking pulses shown in the table in Figure 4 are in a similar manner converted into digits represented by counters A, B and D.

Referring to Figure 5, the A, B and D counters are shown together with the particular digit output lines therefrom required to make up the leading and trailing edge counts of the waves shown in Figures 3 and 4.

The convention used for indicating the digits associated with a particular counter is to afnx a superscript denoting the digit to the capital letter assigned to the counter.

Referring tothe A and B counter columns in Figures 3 and 4 it is noted that the A counter digits to be sensed are A0, A1, A2 and A3; and the digits required to be sensed from the B counter are B0, B1 and B4.

Referring next to the D counter, as will be made clearer later, the only single digit outputs needed are D0, D32 and D523. In addition, three digits or time interval outputs are needed. First interval DO/5 is provided since it defines the first group of equalizing pulses (see Figure 3), then interval Dfi/1l is provided to define the serrated vertical pulses, and finally interval D12/1' is provided to define the second group of equalizing pulses. It should be noted that these time intervals define the vertical sync pulses for both the odd and even fields of a frame.

As further shown in Figure 3, in order to break up a field interval into the period 28 when the vertical sync pulses are generated and the period 29 when the horizontal sync pulses are generated, the counting intervals DO/l" and D13/524 are needed. The interval D/17 is obtained by combining the digital output lines representing D0/5, Di/11 and D12/1" in a logical sum circuit 35 whose output line represents DO/l. As for the output D13/524, since this is a proposition which is true when proposition DO/l" is false, the voltage line Dom is inverted in a tube inverter 36 to obtain voltage line D18/5,

To define the whole-line intervals, as required for the horizontal sync pulse, as contrasted to the half-line intervals required for the vertical sync pulses, a C digit output line is provided from the C counter.

The general logical method of circuit design utilized in the present invention for the counters and associated circuitry will next be considered.

This method utilizes the correspondence between propositions and methods of symbolic logic, and the two valued nature of electrical quantities in impulse work.

In general when a voltage has two possible values, high or low, it can be used to describe the state of a proposition of symbolic logic which itself has two possible values, true and false; or, as referred to in terms of counting, one and zero.

Propositions are represented in the present invention by flip-flops. When a given proposition is true the flip-flop is in one of its states, and when false in the other state.

In accordance with the present invention it is desired to have both the true and false states of the proposition flip-flop capable of being sensed as a relatively high voltage. Hence, output lines are connected to each of the plates of the flipfiop. Likewise it is desirable to be able to trigger a proposition flip-flop to 'either its true or false state by separate input lines, hence, an input line is connected to each of its grids.

In the present invention combinations of capital letters and numbers are usedfor designating the proposition flip-flops themselves. The outputs of the flip-flops are characterized by corresponding capital letters with an appropriate subscript. Since one of the outputs correspondsto the flip-flop proposition being true and the other corresponds tothe proposition being false,` the' latter is distinguished from the former by an a'fxed prime. l On the other hand, the inputs to a ilip-op are designated by corresponding lower case letters with an appropriate subscript. The input for rendering a'ip-ilop false being further characterized by a sub-zero preceding the lower cas letter, l As will be seen, each of the input leads to a proposition flip-flop can be represented by a logical algebra equation. This equation is made up of states of flip-flop propositions (either true or false) which logically govern this input. v

'lakingl the equation which represents the input to a given proposition flip-flop to make it true, for example, the various terms, which represent the true or false states of the governing proposition, are related either by logical multiplication or logical summation operations. `By use of logical nets, to be described, these equations are physically solved. The solution rbeing represented by a relatively high Voltage .level on ag single wire. By connecting this wirektothe right input of the ilip-op, the validity Aof the proposition is automatically determined by the state of the flip-flop. 2

Referring next to Figure 6a, a detailed schematic circuit diagram is shown of a typical wellknown flip-flop circuit used for representing the propositions of the present invention. v The flip-flop circuit here shownv comprises two triodes V1 and V2. The plate of each triode is intercoupled` to the grid of the other by a resistor R in parallel with a capacitor C; The plates of each of the triodes are connected through separate load resistors, like resistor R1 to a positive D.'C. source +B, and the cathodes of the triodes are grounded. The grids of the tubes are joined through separate-grid resistors R2 to a negative bias -E. The flip-flop circuit is provided with triggering circuits associated with each of its grids and output circuits connected to each of its plates.

Whenever a ilip-ilop is considered to 'be in a one state, neon light L, connected in series with a limiting resistor R across the left load resistor R1, lights-up; and when the flip-flop is in a"zerc state, neon light L is out. i Thus it is when tube V1 is in the conductive state that the voltage drop across its plate load resistor R1 enables the neon light L to become energized. A one state of the flip-flop is .thus

indicative of tube V1 being in a conductive state and tube V2 in a non-conductive state. Referring to the outputs from the flip-flop circuit, the one state of the flip-flop is characterized by a high Voltage on the output connected to theplate of the V2 tube simultaneously with a relatively low voltage onthey output connected to the plate of the V1 tube. The zero state is characterized by opposite voltage levels on theplate outputs. 'I-'he circuitry connections for the flip-flops here shown are the onesrequired fori-,thesingle stage which comprises the C counter. i f f are takenfrom the right and` left plates respectively. In order to maintain the swing of the plate voltage between voltage levels En and EL, clamping diodes, such as diodes 32a and 32h associated with the right output C1, are provided on each ,of the output lines. g i s This counter fiip-ilopkeeps track of the halfline counts. Every timev a transfer pulse is fed from the.B counter the Cl flip-flop changes state. This is accomplished by gate circuits 31 and 38 coupled to the left and right grids of the flip-flop respectively. For example, the left gate circuit 31 is coupled by differentiating circuit 39 and attenuatingy diode 40 to the left grid. For this Darticular counting stage, the right plateoutput C1 is connected to one input of theleft gate 31; and the left plate output G1 is connected to one input of the right gate circuit 38. The input transfer pulse TB from counter B is applied simultaneously to the second inputs of each ofthe left and vright gatecircuits'31 and 38. l f- As will be seen from the following part of th descriptions, these gate circuits are typical logical product diode nets.kk In such a circuit, as noted in particular for left gate 31, the inputs `therein are applied on the cathode-ends of diodes 4I and 42 whose plate ends are joined to a common line i 43 which is connected to a positive source through stage circuit, above described, are shown. In line I the regularly recurring transfer pulses TB are shown; inline II the Crpl'ate output -is shownto be initially of a high'voltage; while in line III the C1 plate output is shown to be initially of a 'low voltage. As shown in line IVY.'y whenever both the waveforms C1 and TB are relatively high in potential, Ithe term oc1 is' considered'to pass through the gating circuit asa rectangular pulse similar in waveform to the transfer pulse TB.

In line V the pulse form impressedvon the input to the left rgrid is shown to be essentially theA diiferentiated trailing edge 51a of the rectangularr pulse 0c1f. Itis thus noted that the Hip-flop changes state on the trailing edge of. the 0c1 (or transfer pulse TB) It is also noted that as a result of triggering the left tube off the left plate is now high in potential so thaton occurrence of the next `transferpulse TB, the right gate, in effect, allows the transfer `pulse to passtherethrough and hence 'the diierentiated trailing edge'lb of this latter pulse triggers the flip-flop back` to its original. state.

vBelow ,the cl nip-flop circuitin Figure 6a the coincidence of waveforms at the gates is .signified, using symbolic logic notation, by a productequation. When theftermsI of such an equation are all high in potential the trigger proposition represented by the equation is consideredtgbe effective. Thus the equation which defnes when theCl flip-flop is to bemadegftrue is c1=C1'TB1 l l and the equation which dennes when the'CI flipiiop isrto be made false is oci=C1Ts- The equations for the inputs to the proposition flip-flops are thus a useful key revealing the manner in which the outputs of the nip-flops are interconnected to the inputs.

Referring next to Figures 7a through 7d, the output flip-flops SI, HI, VI and MI, respectively, are shown. These flip-flops are all similar to the one shown in Figure 6a and so they are shown in a simplified manner, indicating mainly the plate output line and the gating circuit to each of the inputs.

Referring first to flip-flop Sl, the right output plate line SI only is required. However, both triggering inputs are required. These are represented herein by right and left gates 45 and 46 controlled by propositions represented by the equations shown below the flip-flop circuit. These equations are obtained in particular by reference to the table in Figure 3. It was previously noted that the timing of the leading edges of the vertical sync pulses generated by the SI flip-nop are denoted by digits B and A1 in the B and A counters respectively during the digit interval DW in the D counter. This is represented in symbolic notation by the logical product D/1"BA1. As for the leading edges of the horizontal sync pulses, they are represented by digits C, B0 and A1 in the C, B, and A counters respectively during the digit interval D18/524 in the D counter. These latter leading edges are symbolically notated by logical product Thus the si triggering equation which makes the Si output' high can be expressed by logically summing the above two logical products.

The plus sign is used for indicating logical summation, known also as the inclusive or operation. Since all changes in the waveforms are to be synchronized with the trailing edge of the timing pulse P, coincidence of this latter pulse is also required at each of the gates as noted by the term P which multiplies the logical sum to complete' the equation.

As for the trailing edges of the sync waveform, it is noted that the trailing edges of the equalizing pulses are defined by digits Bo and A3 in the B and A counters during time intervals DV5 and D12/1'1 defined by the D counter; the trailing edges of the vertical serrated pulses are defined by digits B4 and A2 in the B and A counters durf ing the interval -D/11 of the D counter; and the trailing edges of the horizontal sync pulses are defined by digits C, B1 and A0 during time interval D18/524. Hence the osi triggering equation is denoted by the logical equation:

Referring next to Figure 7b, the horizontal drive flip-flop HI is schematically illustrated along with its input triggering logical equations. Since the horizontal drive pulses are similar to the horizontal sync pulses, the equations are as follows:

h1=CBA1P oh1=CBlAP Note that the counts are exactly the same as the latter portion of the vSI input equations except that no restriction is imposed by the D 12 counter, since' the horizontal drive pulses occur continuously.

In Figure 7c, the vertical drive nip-flop Vl is schematically depicted. rI"he triggering input equations therefore are as follows:

In Figure 7d, the mixing blanking flip-flop MI is schematically illustrated. By reference to the table in Figure 4 and the previous discussion, the leading edges of the output wave therefrom, i. e.. the mi input which triggers the fiip-flop so that its output is high in potential is expressed as:

The trailing edges of the output wave therefrom, i. e., the @mi input which triggers the flipfiop so that its output is low in potential is expressed as:

In Figure 8, a block diagram is shown of the YI flip-nop which generates the D counter inter val DS3/524. As previously noted this time interval is needed to define the interval during which the horizontal blanking pulses are generated. As seen below this ilip-op, the left flip-flop input gate opened at count D32 thus permitting the next TB pulse, corresponding to count D33, to trigger the left output to a high potential. On the other hand the right flip-flop input gate opened at count D523 thus permitting the next TB pulse, corresponding to the D524 count, to trigger the left output to a low potential.

It should be noted that in triggering the YI nip-flop there is a one TB pulse delay between the time the applied D32 term reaches a high potential and the left plate output line DS3/52* reaches a high potential, in that it is the trailing edge of the next TB pulse after the D22 term becomes high that triggers the flip-flop.

Referring next to Figure 9a, the proposition flip-flops AI, A2, and A3, comprising the stages of the A counter are schematically illustrated.

Below the flip-flops the logical equations describe how the outputs of the flip-flops are connected to the inputs to cause the A counter to count through a cycle of five consecutive digits, i. e., have a radix of five.

'I'he counter arrangement is a parallel one in that the P pulses from the pulse generator I0 are applied on all the flip-nop inputs simultaneously. The interconnections of the ilip-iiop outputs, however, only allow certain flip-flops to be triggered by the successive P pulses so as to change their states in an orderly fashion to indicate the successive digit outputs.

In Figure 9b the combinations of the states of the flip-iiops which indicate the digital content of the counter are shown by a table. This table is a binary representation of the digits 0 through 4, herein designated Ao through A4.

The connections of the outputs of the flip-flops to the right input of a particular fiip-iiop, i. e., the input which when triggered will make the flip-nop in question true, are determined by examining the states of all the flip-flops whenever the flip-flop in question is to change from a zero to a one"; and the connections of the outputs of the flip-flops to the left input of a particular flip-flop, i. e., the input which renders the flip-iiop false, are determined by examining the states of all the fiip-iiops whenever the fiip- 13 flop in question is to changefrom a one to a lzero' n y y The coincidence of these flip-flop stateswa're then represented as logical 'products made up of the terms representing'the flip-flop outputs. For example, examine the flip-iiop states' when it is desired to make flip-nop AI true, i. e., have a 1 therein on occurrence of the next P pulse. This occurs when changing from digits A to A1 and A2 to A3. It is noted that a suiiicient condition is that nip-flops Ai and A3 are'both necessarily indicating a 0 state at the same time. Hence, the equation cn=A1'. iaP. Likewise a sufficient condition necessary to make iiip-iiop AI false, i. e., record a 0 therein on occurrence of the next P pulse, is that flip-flop Al be in a true state.' Thus it follows that oa1=A1P.

In a similar manner the conditions necessary to make flip-flop A2 true are that iiip-flop AI be in a true state rand ilip-iiop A2, itself, be in a false state as symbolically noted .by ,a2=A1A2'P. To make flip-nop A2 false, flip-flops AI and A2 must be simultaneously recording a one, i. e., oaz=A1A2P.

It is noted that this latter condition which makes fliplop A2 false is also the one required to make iiip-flop A3 true; hence a3=A1A2P. As for the left input of the A3 iiip-flop, a suiiicient condition required to make iiip-ilop A3 false is that it be previously true. Thus oa3=A3P.

Referring next to Figure 9c, the logical diode nets required to physically solve these triggering equationsare shown. Y l

The solution of oal=A1P vwill first be described. To lsolve this equation, a logical product of terms A1 and P must be obtained as shown in a typical product circuit 44 which is identical to the gate circuit shown in Figure 6c. Here the potentials A1 as obtained from the right plate output of flip-flop AI and P as obtained from the pulse generator Il) are fed into a pair of input diodes 45a and 46a having their plates'interconnected at junction 4l. Junction 41 is then returned to a high potential through a load resistor R4. This circuit is such that whenever either or both of the inputs A1 and P are relatively low in potential, current is drawn from source B-I- through resistor R4, thus keeping junction 41 relatively low in potential. However, whenever both inputs are relatively high in potentiaL'the output line 48 is relatively high. The aclA equation is considered to be solved when this output line 48 is high in potential.

Output a2 is seen to be a product of the same terms dening nar multiplied by an additional term 'A2'. It 4should `be noted that instead of providing a three input product circuit for solve ing the az equation, the output of the two input product circuit 44 is cascaded into oneof the inputs of a second two input product circuit 49 along with the new term A2. Thus the output 50 of the second two inputv product circuit 49 generates the a2 solution. n v *l The output equations naz and as are identical and also include therein the common product dening nal. Hence the output of the two input product circuit 44 is also fed as one of the inputs I into a third two input product circuit 52 along with the new term A2. The output of this third productvcircuit 52 provides both @a2 and a3.

vThe a1 term which is equal to'Ai'AsP is generated as an output from multiplication circuit 56. As will be shortly described, the partial product of terms A1 and A3l occurs again inthe digital output diode net. Hence these two terms `are fedthrough diodes 53r `and 541to aivcommon line 55. However, since this partial product'is `not used as an output as such, or, as will. be shortlyv described, as an input to a logical addi#- tion circuit, no resistor return to potential source B| is supplied for common .line 55.y Instead the output of common line 55 is .combined with the term P in multiplication circuit 5B to generate ai at its output.

The oas triggering solution is obtained by multiplying terms A3 and Pin a separate product network 58. `It should be noted that the over- .flow from the A counter feeds thefBy counter. Hence the diagonal output line 59 from product network 58 also generates this transfer term TA.

The logical net to generate the digitaloutputs required from the A counter as noted in Figure 5 will next be described. As shown in yFigure 9b, digit output A2 iscomprised of ra logical product `made up of the false states of flip-,iiopsAl and A3 together with the true state 'of` iiip-ilop A2. The partial product AiAs was previously generated on common line 55. Hence the voltage on this line along with the term A2 is fed ,into a rst logical product circuit 60 to generate digit output line A2. Digit line Ao isylikewise obtained by a product comprised oi partial product A1A3 as obtained from common line V55mm,- tiplied by the term A2 in asecon'd logical product circuit 6|. The digit output `line A1 -is made up of terms A1, Az', A3 combined inas'separate three input product circuit 52. A3, which is the last one needed, is made up. of a separate product ycircuit comprised. of'terms A1 A2, as shown. Y y f In Figures 10a, 10b and 10c, the counterBis shown. The arrangement of this vcounterfis identical to that for counter A, except that the flip-flops are herein designated BI, B2, B3.;.and the input to the counter which is the carry from counter A is designated TA which is in itself equal to the product AsP (see Figure 9c). The combinations of the states of the B iiipffl-ops repre'- senting their digital count are the sameas in .counter A; and hence the interconnections, as

represented by the input equations, as well as the varrangement of the counter diode net, are the same. In this case, however, the digit outputs provided bythe digit output logical net are yonly B",'Bl and B4. The transfer pulse TB from the ,Bcounter which is comprised of the producto terms TA and Bais generated yon line51. Y 1 g Figure 11 showsA the general breakdown of the D counter. It should be noted that in order vto obtain a simple counter having a radixfor 525, -this-counter^is actually composed of a cascade of counters E, F, and G.

The conversion ofthe D digit outputs,y required as shownin Figure 5, to the-E, F, G digit outputs, is `indicated in Figure l2. Thereit is shown that counter E has ya radix 7 whose output cascades linto counter F having a radix 5, and the output of counter F cascades into counter G having a radix of `15. It is now apparent that just as the Aand B counter digits whentaken together give afradix 25 counter, the E, F and G counterdigits when combined give aradix 525 counter.

Three digit propositions-and three interval propositions are required from this table (Figure l2) in order to denne the D digit and interva Ioutputs shown in Figure 5.

The three digit propositions, as expressed in symbolic notation, are obtained directly fromthe contents of the counters. Thus: l

The digit output line i 

